1. Field of the Invention
The present invention relates to processes involved in the manufacturing of semiconductor devices. More particularly, the present invention relates to methods for testing integrated circuits.
2. Description of the Related Art
As integrated circuit devices grow smaller and smaller, the testing of the integrated circuits presents greater challenges. For example, the shrinkage of transistor sizes to the point that critical dimensions are well below one micron (10−6 m), has resulted in more elaborate and expensive testing fixtures to probe the contacts on the wafer during testing steps.
Semiconductor wafer fabrication involves a series of processes used to create semiconductor devices and integrated circuits (IC's) in and on a semiconductor wafer surface. Fabrication typically involves the basic operations of layering and patterning, together with others such as doping, and heat treatments. Typically, a large number of dies are formed on a wafer using these methods. Many of these dies may have defects occurring during the fabrication process, for example during the patterning of layers, which affect the reliability of the die. Some defects, for example, directly affect the functionality of the circuit resulting in functional failure. Other defects may adversely affect the reliability of the circuit resulting in an early lifetime failure or failure under varying operating conditions.
Conventional manufacturing methods, as illustrated in FIG. 1, include fabrication, wafer sort or probing, assembly or packaging, and testing performed in sequence. As discussed above, the fabrication operation 102 forms the individual dies onto a semiconductor wafer. The wafer is often 300 mm or more in diameter and typically includes a large number of integrated circuits or dies on the wafer. For example, a single wafer may produce 50 to 200 or more identical integrated circuit dies.
Each of the individual dies is then tested to determine its operability, that is, to determine if the chips function in accordance with the design. This step is typically performed at wafer sort or probe 104. During this step the unencapsulated die are tested while still part of the wafer. The wafer prober usually involves a material handling system to transfer wafers from their carriers to a flat chuck and aligns them precisely under a set of fine contacts or probe tips on a probe card. The probe card, provides interconnection between the die pads and a load card which is connected to automated test equipment (ATE). The probe card thus acts as an interface between the metallic pads on the dies and provides connections to the tester. The functional tester or automatic test equipment (ATE) is capable of functionally exercising all of the chip's designed features under software control. Any failure to meet the published specification is identified by the tester and the device is cataloged as a reject. Thus, both good and bad dies may be determined. Bad dies are often marked by either a probe or ink mark at the wafer sort operation.
Next, as illustrated in operation 106, the assembly of the chips takes place. Typically, the wafer is diced, i.e., sawn along “streets” of the wafer to form individual die. The “streets” or scribe lines lie between each die and are used as cutting lines during the wafer sawing operation. During the assembly step, the die is separated from the wafer and packaged to form a device that can be attached and electrically connected to a printed circuit board, for example. Thus, the assembly operation includes a number of sub-steps such as wafer sawing, die attachment, and bonding.
During the package testing operation 108, a final opportunity is presented to test the functioning of the chips (die). This is also referred to as final test. Typically a material handling system transfers packaged dies from their carriers and loads them into contacts or sockets on a load board. The functional tester or automatic test equipment (ATE) then functionally exercises the chip's designed features under software control to identify defective die.
Unfortunately, the wafer probe operation is a very delicate and time consuming operation requiring a great deal of skill. As discussed, electrical contacts between the metallic pads on the dies positioned on the wafer and the tester is achieved by using a probe card. The probe card is a customized printed circuit board designed to match the bonding pad geometry of each die and connect it to the test equipment. The wafer can then be moved either manually or automatically by the machine in both vertical and horizontal directions. The probe card includes thin metal probes which make the connection between the card's circuit, i.e., the printed circuit board portion of the probe card, and the die bonding pads. By lowering these probes onto the metallic contact pads of each die, an electrical connection is made for functionally exercising the die under a test program generated by the tester. Since probe cards must be custom built for each new integrated circuit design to match the particular metallic pad configuration for that design, expenditures for probe cards can be substantial. For example, at the time of the drafting of this specification, probe cards costs are as much as eighty thousand dollars or higher.
Unfortunately, the production run of the dies may be of a small volume, and thus building test fixtures (such as probe cards) that are specific to the design may not be economically justified. This is particularly the case for some Application-Specific Integrated Circuit (ASIC) manufacturing flows, and for prototype designs.
For example, the total anticipated production volume of the ASIC may be only a few thousand units. If the expected yield at wafer probe is on the order of ninety percent, it would make far more sense to skip the wafer probe test step entirely in favor of testing the die in its packaged form.
Once the die has been assembled in its final packaged form, the functioning of the die may be performed at the final test step. Final testing does not require the dedicated, custom fixtures such as probe cards for testing, since many designs which are quite different in die form may still share the same package and the same arrangement of power and ground planes in the package.
Unfortunately, skipping the wafer sort step results in the loss of information regarding the original location of the die a particular wafer. For example, it is quite common to have ‘rogue’ wafers appearing from time to time in an otherwise normal wafer lot. A rogue wafer might yield very poorly at the wafer probe step, i.e., falling far outside the specifications due to a process irregularity, and might result in a decision that the entire wafer represents a process excursion that should be completely contained and not shipped to the customer. But if the wafer sort step was skipped, such information pertinent to all of the dies on the wafer would not otherwise be available at the final test step. That is, a slightly depressed yield at final test will not provide sufficient information to determine that all units built from a given wafer should be rejected, even if individual package die could be correlated to a particular wafer.
Accordingly, it is desirable to provide a more effective and economical screening and evaluation method for detecting defects in die.